1. Field of the Invention
The invention relates to the field of computer systems. More specifically, the invention relates to the area of memory management.
2. Background Information
Memory addressing schemes often use a technique called paging to implement virtual memory. When using paging, the virtual address space (i.e., the address space generated by either the execution unit of a processor or by the execution unit in conjunction with a segmentation unit of a processor) is divided into fix sized blocks called pages, each of which can be mapped onto any of the physical addresses (i.e., the addresses that correspond to hardware memory locations) available on the system. In a typical computer system, a memory management unit determines and maintains, according to paging algorithm(s), the current mappings for the virtual to physical addresses using one or more page tables.
Upon receiving a virtual address from the execution unit of a processor, typical memory management units initially translate the virtual address into its corresponding physical address using the page table(s). Since the page table(s) are often stored in main memory, accessing the page tables is time consuming. To speed up the paging translations, certain computer systems store the most recently used translations in a translation look-aside buffer or TLB (a faster memory that is often located on the processor). Upon generating a virtual address requiring translation, the memory management unit first searches for the translation in the TLB before accessing the page table(s). If the translation is stored in the TLB, a TLB "hit" is said to have occurred and the TLB provides the translation. However, if the translation is not stored in the TLB, a TLB "miss" is said to have occurred and a page miss handler is invoked to access the page tables and provide the translation.
A number of different techniques are used for implementing page miss handlers, including: 1) hardware on the processor to access the page table(s) (referred to as a "hardware page miss handler"); 2) operating system routine(s) whose execution controls the accessing of the page table(s) (referred to as a "software page miss handler"); etc. Certain systems use multiple techniques for handling TLB misses. For example, one system uses a hardware page miss handler to access a hashed page table and a software page miss handler to control the walking of non-hashed page table(s). Thus, the phrase "page miss handler" is used herein to refer to any technique for providing a translation when another address translation unit cannot provide the translation.
When using a software page miss handler, a TLB miss causes the processor to interrupt execution of the current process, store the interrupted process' execution environment (i.e., the information necessary to resume execution of the interrupted process), and execute the software page miss handler to determine the paging translation. Execution of the software page miss handler results in the generation of the translation, and typically the installation of that translation into the TLB. Upon completion of the software page miss handler, the processor resumes execution of the interrupted process.
Certain computer systems are now further dividing the virtual address space into regions of virtual address space using address extensions, where each region can contain one or more pages. Each region is identified by a region identifier (also termed an "address space identifier"). In certain computer systems, N bits of the virtual address are used to identify 2.sup.N different regions of virtual address space. Each of the 2.sup.N regions may be utilized for any number of different uses. Furthermore, each of the variety of different uses for different regions of virtual memory may have different memory accessing characteristics (e.g., local, global, etc.)
The installation of translations into the TLB is typically performed using one or more TLB installation registers (e.g., a page miss handler stores the translation in the TLB installation register(s) and instructs the processor to install the translation in the TLB). The TLB installation register(s) often include a region identifier field, a translation attribute field, a virtual page number field, and a physical page number field. The translation attribute field is used to store data identifying various characteristics of the page being accessed (e.g., access protection, etc.).
Upon recognition of a page miss, typical computer systems: 1) load the virtual page number and region identifier into the TLB installation register(s); and 2) invoke the page miss handler(s) to load the physical page number and attributes into the TLB installation registers. Although the attributes for pages in a region can vary, the majority of pages in a region often have the same attributes. However, the page handler(s) must load the attributes for each page in a region each time a translation must be installed. Since TLB fills occur at a much higher rate than other types of events (e.g., exceptions, interrupts, operating system calls, etc.), it is desirable that the page miss handler(s) be as streamlined as possible.